Ultra-low-power 2D DCT/IDCT architecture using hybrid GDI-PTL adders and Wallace tree multipliers

Abstract

The discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) are widely used in image and video compression, but their hardware implementation requires substantial arithmetic activity and can increase power and area. This work addresses this issue by developing an ultra-low-power, full-precision 2D DCT/IDCT architecture that combines hybrid gate diffusion input and pass transistor logic (GDI-PTL) full adders with Wallace tree multipliers. The objective is to reduce arithmetic power and area while preserving reconstruction fidelity. The proposed architecture uses separable row- and column-wise processing, fixed-point coefficient representation, pipelining, and fine-grained clock and data gating. The register-transfer level (RTL) design is verified using Verilog and MATLAB, and the application specific integrated circuit (ASIC) implementation is synthesized in Cadence Genus and physically implemented in Cadence Innovus Stylus at 45 nm. Post-layout results show a core area of 58,540.8 µm², total power of 2.874 mW at 100 MHz, and a critical data-path delay of 0.261 ns. Image reconstruction is evaluated using compression ratio (CR), peak signal-to-noise ratio (PSNR), and structural similarity index measure (SSIM), demonstrating that the architecture maintains high reconstruction quality while reducing hardware power consumption.